1. Field of the Invention
The present invention concerns a new and improved isolation structure for MOS devices and the process of preparing the same.
More generally the invention concerns the fabrication of bipolar and unipolar semiconductor devices of the MOS type (Metal-Oxide-Semiconductor), be they linear integrated circuits or digital integrated circuits of low (SSI), medium (MSI), large (LSI) or very large (VLSI) scale of integration. For the sake of a greater descriptive simplicity, in the instant disclosure, though referring generically to MOS devices or processes of the N channel type (NMOS), it is intended, obviously, to include the various known MOS technologies, that is: P channel (PMOS), complementary (CMOS) and variations thereof.
2. Description of the Prior Art
Modern fabrication processes for semiconductor devices of the MOS type, often referred to as "MOS processes", utilize special fabrication techniques developed for improving the geometry of the tormented profile of the surface of the devices and for allowing ever greater degree of integration. A main objective of such techniques being the elimination (or the smoothing) of sharp edges in the layer of silicon oxide used for defining the areas wherein the active and passive components of the device are formed and which edges bring about points of great fragility of the overlying layer of metallization. Processes such as the Locos process of Philips and the Planox process of SGS are well known fabrication processes for semiconductors of the MOS type;
Such processes are amply described in literature, and a description thereof appears in the book by H. Lilen "Principles et applications CI/MOS" Editions Radio, Paris, 1972, from pag. 61 to pag. 65.
In particular, the Planox process is disclosed in the publications by F. Morandi-IEDM Techn. Dig. Session 18, Oct. 1969 and by T. C. Wu-W. T. Stacy and K. N. Ritz-Journal of Electrochemical Society, 130, 1563 (1983).
A crucial stage of the Planox process is the formation of the field oxide, that is of the dielectric structure which isolates the various active and passive elements forming the MOS device.
Such a structure is formed by growing a layer of oxide of suitable thickness, commonly about 5000-15000 .ANG., on areas of the substrate single crystal silicon defined by removing with photolithographic techniques the masking layer of silicon nitride from the desired areas. The remaining nitride layer effectively protects from oxidation the areas where will be later formed the active and passive elements of the integrated circuit.
The steps which are formed in growing the oxide of the isolation structure are lower because the growth of the thick oxide layer on the uncovered areas progresses for about half of its thickness below the original surface of silicon thus resulting in "buried" oxide for about half of its thickness.
Indeed, because of the way the field oxide is formed, its lateral edges are not vertical but decisively swaged. That is, being the process of oxidation of silicon in the unmasked areas essentially a diffusion process, oxidation tends to progress, though at a rapidly ever decreasing rate, also immediately underneath the masking nitride layer, even though the latter being impervious to vapor and oxygen, that is beyond the geometrical limits of the edges of the layer itself.
Therefore the thick (field) oxide obtained by the Planox method shows, in cross section, a characteristic tapering of the edges which in view of its shape it is often indicated by the name Planox's "beak".
The partial "burying" of the isolation structure, that is of the thick (field) oxide and the swaging of the edges thereof produce a morphology characterized by small and less steep steps greatly facilitating the preparation of the layer of polycrystalline silicon and of the subsequent metallization and/or isolation layers.
Nevertheless the amount of swaging, or the length of the Planox's beak, must be carefully limited because, though improving the capacitance and junction breakdown voltage or BV.sub.xj characteristics, it causes remarkable geometrical problems in so far as it decreases the adjacent active areas and thence imposes a limit to the reduction of the line width, problems which are strongly felt in pursuing ever increasing degrees of integration and thence of miniaturization. There is furthermore a whole series of effects well known to the expert of the field, with respect to which the structure and configuration of the field oxide layer in MOS devices should be such as to satisfy the following requirements:
(a) determining a threshold voltage of the parasitic field effect transistor formed in connection with such oxide by the interconnecting strips of polycrystalline silicon or of metal sufficiently high in order that such a parasitic transistor does not conduct when on the "gate" are applied the working voltages of the device;
(b) determining an avalanche breakdown voltage of the junction certainly higher than the maximum voltage of operation of the device;
(c) preventing "Reach-through" or V.sub.PT phenomena that is preventing that the depletion region of a reverse biased junction extend that much as to reach the depletion region of another uncorrelated junction which is held to ground;
(d) determining low junction capacitances along the edge of the area;
(e) determining steps as small and with as less slope as possible; and
(f) requiring the minimum area as possible.